The present invention relates to an arrangement of a plurality of current source cells forming an integrated circuit on a semiconductor printed circuit board and a method of selecting current source cells, and more specifically to a current source cell arrangement suited for minimizing signal distortions of a current addition type Digital-to-Analog (D/A) converter, a current source cell selection method and a current addition type D/A converter.
Many electronic devices such as cellular phones use a current addition type D/A converter that converts a digital signal into an analog signal. The current addition type D/A converter, if its differential non-linear error is large, distorts a converted analog signal.
FIG. 10 is a layout diagram showing a conventional current source cell arrangement of the current addition type D/A converter. The current addition type D/A converter for mounting on LSIs is manufactured by arranging a large number of current source cells in matrix. FIG. 10 shows a configuration of the converter having an array of 240 current source cells 1 (16 rowsxc3x9715 columns) arranged in 15 column units each consisting of 16 current source cells to represent higher 4-bit MSBs (most significant bits) of an 8-bit current addition type D/A converter.
In the following explanation of the current source cell matrix, a number xe2x80x9caxe2x80x9d in matrix (a, b) represents a xe2x80x9crow numberxe2x80x9d and a number xe2x80x9cbxe2x80x9d represents a xe2x80x9ccolumn numberxe2x80x9d unless otherwise specifically stated.
When a conventional current source cell matrix of such a configuration is to be operated as a D/A converter, the following arrangements are made. For example, if one unit of the MSB cell is to be represented by a current value of 16 current source cells, xe2x80x9c2xe2x80x9d units of MSBs can be represented by selecting 32 current source cells. Similarly, xe2x80x9cNxe2x80x9d MSBs can be represented by selecting 16xc3x97N current source cells.
At this time, according to the conventional layout of the current source cells, a vertical column is selected to electrically connect the 16 current source cells. For example, (1, 1) to (16, 1) are selected to represent one unit of MSB and the total current value of that one unit is used as a signal output for MCELL1. Next, (1, 2) to (16, 2) are selected to represent one unit of MSB and the total current value of that one unit is used as a signal output for MCELL2. The similar process is carried out until the current source cells (1, 15) to (16, 15) are connected vertically, thus producing signals MCELL1 to MCELL15. In this way, to simplify the connection of one unit of MSB, the current source cells to be summed up are arranged in one direction (column direction).
The layout of the current source cells 1 shown in FIG. 10 are assumed to have the same capacities. If there are variations in capability among the current source cells, the capability variations are reflected on the output signals from MCELL1-15, distorting the output signals from the D/A converter.
The capability variations of the current source cells are those with a certain tendency, rather than random variations. This is considered to result from the LSI manufacturing process. When for example the weight of the current capability of the current source cell (1, 1) at the upper left corner is xe2x80x9c1xe2x80x9d, the current capability increases at a rate of 2% in the vertical direction and at a rate of 3% in the lateral direction as indicated by figures in the cells of FIG. 11, exhibiting a certain tendency of variations.
In such a current source cell matrix, when the outputs of the 16 vertically arranged current source cells are electrically connected, their total current value is xe2x80x9c18.4xe2x80x9d in the smallest MCELL1 and xe2x80x9c25.12xe2x80x9d in the largest MCELL15 for each MSB cell 4.
Due to the process variations that occur when the D/A converter is manufactured in the form of LSI, the current values of constitutional current source cells differ greatly between the ends of the current source cell matrix, making it impossible to secure linearity. Particularly in the current addition type D/A converter that controls the output value by the current value, a differential non-linearity (DNL) error and an integral non-linearity (INL) error, measures of its linearity characteristics, deteriorate.
Although in the above conventional example a D/A converter has been described, the same problem occurs also when a plurality of constant current sources are manufactured on semiconductor IC circuits. When constant current sources are provided on semiconductor IC circuits, because a required output current cannot be produced by one current source cell alone, outputs of a plurality of current source cells are parallelly connected to function as a constant current source with a predetermined output. However, if a large number of current source cells provided as shown in FIG. 10 are divided into groups each consisting of a predetermined number of cells and, in each group, the output currents of the cells are added up to manufacture a plurality of constant current sources with the same outputs, it is difficult to make the outputs of these constant current sources equal, resulting in variations.
The present invention has been accomplished to solve the problems described above and provides a current source cell arrangement, a current source cell selection method and a current addition type D/A converter, in which current value errors in the current sources due to process variations are reduced by improving the layout of the current source cells to improve a linearity and therefore characteristic of the current sources.
To solve the above problem, this invention according to the first aspect of the invention provides a current source cell arrangement which comprises: a plurality of current source cells each having a predetermined current value, the current source cells being arranged in matrix; wherein two or more of the current source cells in the current source cell matrix are combined to form constant current sources each having a predetermined current value; wherein the current source cell matrix is divided into a plurality of blocks arranged symmetrically with respect to a center of the matrix; wherein the constant current sources are formed by combining equal numbers of the current source cells selected in a row or column direction from each block.
According to the second aspect of the invention, the invention provides a current source cell arrangement in which the current source cell matrix is divided point-symmetrically with respect to a center of the matrix.
According to the third aspect of the invention, the invention provides a current source cell arrangement in which the current source cell matrix is divided line-symmetrically with respect to a center of the matrix.
According to the fourth aspect of the invention, the invention provides a current source cell arrangement in which the current source cell matrix is divided radially with respect to a center of the matrix.
According to the fifth aspect of the invention, the invention provides a current source cell selection method for forming constant current sources each having a predetermined current value by combining two or more of a plurality of current source cells, wherein the plurality of the current source cells each having a predetermined current value are arranged in matrix, the current source cell selection method comprising the steps of: dividing the current source cell matrix into a plurality of blocks arranged symmetrically with respect to a center of the matrix; and selecting an equal number of the current source cells in a row or column direction from each of the divided blocks and combining them to form the constant current sources.
According to the sixth aspect of the invention, the invention provides a current source cell selection method in which the current source cell matrix is divided point-symmetrically with respect to a center of the matrix.
According to the seventh aspect of the invention, the invention provides a current source cell selection method in which the current source cell matrix is divided line-symmetrically with respect to a center of the matrix.
According to the eighth aspect of the invention, the invention provides a current source cell selection method in which the current source cell matrix is divided radially with respect to a center of the matrix.
According to the ninth aspect of the invention, the invention provides a D/A converter which has the current source cell matrix based on the current source cell arrangement according to any one of claims 1 to 4 or the current source cell matrix based on the current source cell selection method according to any one of claims 5 to 8, wherein the constant current sources constitute MSB units representing higher order bits of a digital input, and current values of a plurality of the constant current sources selected according to a decoded value of the digital input are added up to produce an analog output.
According to tenth, the invention provides a D/A converter in which LSB units representing lower order bits of the digital inputs are each formed of at least one of the current source cells.
According to the current source cell arrangement and the current source cell selection method of this invention, if there are capability variations among the current source cells due to manufacturing process variations, these variations can be canceled because the capabilities of the current source cells located at symmetric positions are summed up. Hence, the outputs of the constant current sources are made equal with high precision.
Further, when the current addition type D/A converter is formed by using the constant current sources described above, the degradation of the differential non-linearity (DNL) error and integral non-linearity (INL) error, both representing linearity characteristics, can be reduced, thus realizing a high-precision D/A conversion performance.